The continuous increase of IC integration level requires the size of a device to be continuously scaled down. However, sometimes the operation voltage of an electrical appliance remains constant, which results in a continuous increase of the electric field strength inside a practical MOS device. High electric field causes a series of reliability problems, and leads to degradation in performance of the device.
The parasitic series resistance between the source/drain regions of an MOSFET will lead to the reduction of the equivalent operating voltage. In order to decrease the contact resistivity as well as the source-drain series resistance, a deep submicron small sized MOSFET usually employs a silicide as the dopant source technique (SADS), i.e., usually employs a metal silicide in direct contact with a channel as the source/drain of the MOSFET. Such a metal silicide source/drain MOSFET is also referred to as a Schottky barrier source/drain MOSFET. As shown in FIG. 1, a substrate 10 is divided by a shallow trench isolation (STI) 20 into a plurality of active regions with a channel region 14 included therein, a gate structure 40 and a cover layer 50 on top of it are formed on the substrate 10, isolation spacers 60 are formed on opposite sides of the gate structure 40, a metal silicide source/drain region 30 is formed in the substrate 10 on one side of each of the spacers 60, and the source/drain region 30 is in direct contact with the channel region 14. Wherein the substrate 10 may be a bulk silicon, or may also be a silicon-on-insulator (SOI) comprising a silicon substrate 11, a buried oxide layer 12 and a thin silicon layer 13, or may further be a compound semiconductor material such as SiGe, etc. As compared to a conventional MOSFET with a highly doped source/drain, such a Schottky bather source/drain MOSFET does not need ion shot into source/drain and subsequent activation, the process is simpler, the contact resistance is smaller, and the electrical performance is superior.
It should be noted that, in FIG. 1 and the subsequent Figs., for the sake of convenience to indicate, the STI 20 between the bulk silicon substrate 10 and the SOI substrate (11, 12 and 13) is just a schematic isolation, and not a real adjacency or contact.
The driving capability of the metal silicide source/drain MOSFET is controlled by the Schottky barrier height (SBH) between its source and channel. As the SBH decreases, the driving current increases. Results of a device simulation show that when the SBH decreases to about 0.1 eV, the metal silicide source/drain MOSFET will achieve the same driving capability as the conventional MOSFET with highly doped source/drain.
As shown in FIG. 2, it is a schematic view of a method to use the silicide as the dopant source technique (SADS) to decrease the SBH. Firstly, as shown in FIG. 2A, ions such as boron (B), arsenic (As) and the like are shot into a silicide film 30; next, as shown in FIG. 2B, annealing is performed at 500 to 850° C. to cause ions to segregate at the silicide/silicon interface (i.e., the interface between the source/drain region 30 and the thin silicon layer 13/channel region 14), forming an activated dopant segregation region 70, as shown by the dopant segregation region 70 represented by the hatched part. The dopant segregation region 70 leads to the decrease of the SBH between the source and the channel, thereby improving the driving capability of the device; at the same time, the damage to the silicide film induced by ion implantation is also completely or partly repaired due to the annealing. Since it is necessary to anneal at a high temperature to cause the doped ions to segregate, such an SADS technique requires that the silicide film (the metal silicide source/drain 30) can withstand a high temperature annealing without degradation (agglomeration), namely, the silicide film needs to possess enough thermal stability.
However, after a continuous downscaling of the MOSFET, the thermal stability of the originally relatively thick metal silicide source/drain film 30 will become poor. After a reduction in size, the channel 14 becomes short, and the metal silicide source/drain film 30 will also have to become thin accordingly in order to better control the short channel effect, but the thinned silicide film 30 shows a poor thermal stability during the annealing, and is easy to agglomerate, resulting in a drastic increase in resistivity. Since in the above mentioned SADS method for decreasing the SBH, the silicide film cannot withstand the high temperature needed to give rise to dopant segregation at the silicide/silicon interface, it is impossible for the current metal silicide source/drain MOSFET to effectively decrease the SBH.
Furthermore, when a gate oxide layer continues to be thinned as the downscaling of the MOSFET, the accompanying tremendous electric field strength will cause the breakdown of the oxide layer, forming a leakage path through the gate oxide layer and destructing the insulation of the gate dielectric layer. For reducing the leakage of the gate, a high-k gate dielectric material instead of SiO2 is employed as the gate dielectrics. However, the high-k dielectrics is incompatible with the poly-silicon gate process, and therefore the gate is often made of a metal material.
Illustrated in FIG. 3 is a schematic drawing of the “gate last” process employed in forming such a structure with the high-k gate dielectric material and the metal gate currently. Over a channel region of a substrate 10 with a shallow trench isolation (STI) 20 is formed a dummy gate structure (not shown), around the dummy gate structure is formed an isolation spacer 60, on side of the isolation spacer 60 is formed a metal silicide source/drain region 30, on the whole structure is covered with an interlayer dielectric layer 80, the dummy gate structure is removed, in openings left in the interlayer dielectric layer 80 are sequentially filled with a high-k gate dielectric material 41 and a metal gate 40 to form the final gate structure (A dummy gate is first deposited, and then a metal gate is formed, therefore such a process is referred to as the gate last process, wherein usually after depositing the high-k gate dielectric material, a high temperature annealing is also performed to eliminate defects between high-k gate dielectric material and the channel), etching is performed at a position in the interlayer dielectric layer 80 corresponding to the source/drain region 30 to form a contact hole, and in the contact hole is deposited a metal contact part 90. In such a device structure, there is a spacing between the contact hole and the isolation spacer, and there is a distance between the metal silicide source/drain 30 and the gate structure, i.e., there is neither a metal silicide nor an extended region of the highly doped source/drain below the isolation spacer 60, which will cause a significant and unbearable source/drain parasitic resistance. Such a parasitic resistance and capacitance in the MOSFET structure will increase the RC delay of the device, reduce the switching speed of the device, and thereby greatly affect the performance of such a metal silicide source/drain MOSFET. Consequently, reduction of the parasitic resistance and the parasitic capacitance between the gate and the source/drain is critical to decrease the RC delay.
In addition, since in the SADS technique the metal silicide source/drain region 30 is formed before the high temperature annealing (not only the high temperature annealing for causing dopant segregation, but also the annealing for eliminating the defects between high-k dielectric material and channel), the integrality of the metal silicide source/drain 30 will be deteriorated during the high temperature annealing, i.e., agglomeration may occur for the metal silicide film. The poor thermal stability of silicide will make it impossible to use the SADS technique to decrease the SBH.
In summary, the metal silicide source/drain MOSFET manufactured by gate last process is regarded as the next generation sub-20 nm CMOS structure. The prior SADS method for decreasing the SBH between the source and the channel region to improve the driving capability may not be implemented for being unable to withstand the high temperature annealing when the channel is shortened and the metal silicide film is fairly thin. Furthermore, it is an important point that in a conventional device, below the isolation spacer there is neither a metal silicide nor an extension of the highly doped source/drain region, and thus leading to significant source/drain parasitic resistance and capacitance, which unfortunately increases the RC delay time of the device, and reduces the switching speed of the device.